The present disclosure relates to non-volatile storage.
Semiconductor memory has become increasingly popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. With flash memory, also a type of EEPROM, the contents of the whole memory array, or of a portion of the memory, can be erased in one step, in contrast to the traditional, full-featured EEPROM.
Both the traditional EEPROM and the flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the drain and source diffusion regions. A control gate is provided over and insulated from the floating gate. The threshold voltage (VTH) of the transistor thus formed is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its drain and source is controlled by the level of charge on the floating gate.
In a NAND architecture, memory cells are arranged as NAND strings. A NAND string includes memory cells (each including a floating gate) connected in series over a substrate. At each end of the NAND string there is a select transistor (also referred to as a select gate). One of the select transistors (source side select transistor) connects/disconnects the NAND string to a source line that is common to a large group of NAND strings. Each NAND string is associated with one bit line. The other select transistor (drain side select transistor) connects/disconnects its NAND string to a bit line. In one approach, a memory cell on a NAND string may be read by applying a voltage to its control gate and sensing a signal on the bit line.
Typically, a program voltage VPGM applied to the control gate during a program operation is applied as a series of pulses that increase in magnitude as programming progresses. In one possible approach, the magnitude of the pulses is increased with each successive pulse by a predetermined step size, e.g., 0.2-0.4 V. VPGM can be applied to the control gates of flash memory cells. In the periods between the program pulses, verify operations are carried out. That is, the programming level of each element of a group of cells being programmed in parallel is read between successive programming pulses to determine whether it is equal to or greater than a verify level to which the element is being programmed.
After a given memory cell on the word line selected for programming reaches its intended threshold voltage, programming may be inhibited for that memory cell. In one approach, programming is inhibited by applying an inhibit voltage to the bit line associated with the NAND string. The voltage applied to the gate of the drain side select transistor should be low enough to keep the transistor off, such that the channel of an inhibited NAND string may float. Likewise, the voltage applied to the gate of the source side select transistor should be low enough to keep the transistor off, such that the channel of an inhibited NAND string may float. Also, a voltage is applied to control gates of unselected memory cells, which boosts the voltage in the channel region of the memory cells on inhibited NAND strings. This boosted channel voltage helps to reduce or eliminate program disturb.
However, it is possible for the channel voltage of the inhibited NAND strings to drop, which can result in program disturb. One possible reason for the drop in channel voltage is leakage of current from a boosted channel. For example, the current could leak across the channel of either select transistor.
One type of leakage is due to punch-through conduction across a select transistor. Punch-through conduction may occur due to the difference in the drain to source voltage across the channel of a select gate transistor. As memory arrays continue to scale down in size, the channel length of select gate transistors is getting shorter. Therefore, short channel effects such as punch-through conduction may become more problematic.
Another type of leakage from the channel of inhibited NAND strings may arise due to drain induced barrier lowering (DIBL). DIBL may cause the VTH of the select transistors to drop. If the VTH of a select transistor of an inhibited NAND string is lowered enough, it may turn on, at least weakly. If this happens, then current may leak from the boosted channel across the channel of the select transistor, thereby discharging the voltage of the NAND string channel. Consequently, program disturb could occur.
Gate induced drain leakage (GIDL) is another problem that may cause program disturb. GIDL refers to charge carriers leaking into the channel from a select transistor as a result of a voltage applied to the gate of one of the select transistors. These charge carriers (e.g., electrons) may be accelerated in an E-field in the channel of the NAND string. Program disturb may result due to hot carrier injection of the electrons from the channel to a floating gate of a memory cell.
It is desirable to prevent or reduce program disturb, which may arise from a variety of causes including, but not limited to, punch-through conduction, DIBL, and GIDL.